In general terms, integrated circuits are fabricated by forming a layer, modifying the formed layer in same manner, such as by etching it, and then forming additional layers on top of it. As the layers are formed, different structures of the integrated circuit are created. During the course of fabrication for the integrated circuit, millions of structures are so formed. If even one of the structures is not formed correctly, it is possible that the integrated circuit will not function properly. Thus, great care is exerted to ensure that all of the structures on the integrated circuit are properly formed.
One method of ensuring that the structures are properly formed is to inspect the integrated circuit. By inspection it is meant that the shape of the structure is observed, typically through some process that can detect shape, such as an optical inspection or an inspection with an electron microscope, such as a scanning electron microscope. Such inspections are generally referred to as visual inspections herein, even though they may not be, and typically never are, conducted with the naked eye.
Visual inspections may be performed at various points in time during the fabrication process. For example, a visual inspection can be performed at the end of the fabrication process. However, at that point, many of the various layers and the structures which are formed thereon can no longer be seen by an inspection method that doesn't destroy the integrated circuit. Thus, it is generally desirable to inspect the integrated circuit at several different points during the fabrication process.
Unfortunately, several factors tend to dramatically increase the number of inspections that could be performed. For example, one factor is the number of layers that are used in modern integrated circuits. If an inspection is performed after the formation of each layer, then a significant number of inspections is required. In addition, modern integrated circuits use structures that are fashioned to be smaller and smaller as fabrication techniques improve. Thus, there are an ever increasing number of structures that could be inspected on each level.
As the number of individual inspection sites increases, so too does the amount of time that an inspection requires. For example, it is not unusual for an electron microscope inspection of a substrate on which integrated circuits are formed to require ten hours or more. Such time requirements have placed a severe burden on the throughput of integrated circuit processing.
One trend in the integrated circuit fabrication industry is the general increase of systematic defects that are often design dependent or layout dependant. Examples of these types of systematic defects include co-incident metal corners, stacked vias, vias on large metal lines, and electrically conductive lines that require optical proximity correction. These systematic defects are becoming generally more common than the traditional random defect mechanisms, and tend to be much more susceptible to process excursions such as alignment or equipment control.
What is needed, therefore, is a system by which integrated circuits can be adequately inspected, but which does not require such a great length of time.